As semiconductor manufacturers seek to increase the speed of microelectronic devices, strained silicon and crystal lattice engineering are increasingly relied upon to adjust the properties of semiconductor materials. Strained silicon is a layer of silicon in which the silicon atoms of a crystal lattice are stretched or compressed beyond their normal inter-atomic distance. This can be accomplished by aligning the atoms in a silicon layer with atoms of another material having a crystalline structure with atomic spacing larger than or smaller than that of silicon. For example, if silicon atoms are aligned with a silicon-germanium structure, where the atoms are arranged a little farther apart than are silicon atoms alone, the links between the silicon atoms become stretched. Moving these silicon atoms farther apart reduces the atomic forces that interfere with the movement of electrons through a semiconductor and thereby provides better mobility of electron carriers. On the other hand, reducing the distance between atoms has the effect of reducing atomic forces that interfere with the movement of holes. By stressing semiconductor materials to achieve the desired mobility, semiconductor performance can be improved.
The crystal lattice of a semiconductor region may be stretched or may be compressed to adjust electron and hole mobility. This distinction is sometimes made using the term stress to refer to a compressed lattice structure and strain to refer to a stretched lattice structure. The embodiments and examples contained herein are described using the terms compressive stress to refer to a compressed lattice structure and tensile stress to refer to a stretched lattice structure. Stress and strain are both used to generally refer to both compressive and tensile stresses, and such terms are used interchangeably herein.
Silicon can be stressed by several methods. One approach involves the use of a capping layer to induce stress in silicon of an adjacent lower layer. Depending on the material used for the capping layer, the magnitude and type of stress induced (tensile or compressive) may be adjusted by modulating the deposition conditions, such as temperature. Standard lithography patterning techniques may be used to selectively deposit a capping layer over a target region to induce stress.
Another approach involves epitaxially growing a silicon layer over a substrate layer of silicon-germanium. As silicon atoms bond with silicon-germanium atoms, the silicon is formed to match the lattice structure of the silicon germanium layer. In this manner, the lattice structure of the silicon is constructed in a stretched form.
Another approach is to form embedded stressors, such as source and drain regions of a MOSFET, in a semiconductor to induce stress in the region between the embedded stressors. The magnitude and type of stress induced may be adjusted by selecting various materials for the embedded stressors and adjusting the epitaxial deposit conditions.